1. Field of the Invention
The present invention relates to general purpose digital data processing systems, and more particularly to such systems that employ shared memories accessed simultaneously by a plurality of users.
2. Description of the Prior Art
In most general purpose digital computers, it is desirable to have a computer storage system which can efficiently return data from a main memory. The computer storage system may be comprised of a shared memory resource. The concept of using a shared memory resource results from the design of general purpose digital computers, wherein often times additional memory resources, such as memory modules, are added at later points in time. In multi-processor computing systems, multiple requestors can request access to the same shared memory resource. Typically, these memories are divided into segments wherein the segments are mapped contiguously throughout the address space. Each of the multiple requestors can request access to the same memory segment simultaneously. As a result, requests not able to be serviced must be queued until they can be processed by a memory controller managing the requests. This can have the unfortunate result of decreasing overall system performance. It is desirable therefore to minimize queuing times to ensure maximum overall system performance.
One approach to solve this problem is to add additional queuing structures to support a plurality of requests. For example, if several instruction processors executing programs are utilizing the shared memory resource, adding additional queuing structures would reduce the backlog of queued requests. In one example, in a system utilizing a shared memory resource of 128 megawords of memory, four separate queuing structures may be added, each associated with a particular segment. Of the 27 bits necessary to access the 128 megaword shared memory resource, the two most significant bits, bits 26 and 27, may be used to select between the four segments, and the remaining bits, bits 1-25, used to address a particular word. If the 26th and 27th bit select between the four segments, a separate queuing structure is associated with each 32 megaword memory segment. Utilizing four queuing structures rather than one can increase system throughput by minimizing queuing or wait time. However, the additional queuing structures still do not prevent a backlog of queued requests if several instruction processors, for example, are executing programs resident in the same memory segment. This is because a disproportionate percentage of the requests will be directed at the same segment. That is, if two separate instruction processors are executing programs resident in the same 32 megaword memory segment, a backlog of queued requests could result since only one queuing structure serves the 32 megaword memory segment. This backlog of queued requests would therefore decrease overall system performance.
Another approach which has been used is to associate a cache memory with each individual queuing structure. While this approach can improve system performance by increasing the cache hit rate, a backlog of queued requests can still result if a disproportionate percentage of the requests are directed at the same memory segment. Thus associating the cache memory with each individual queuing structure would still not improve overall system performance.
Another disadvantage is that within the shared memory resource, multiple bit failures can occur. When the address space is mapped contiguously, as with the above approach, these multiple bit errors can be difficult to correct with known parity checking algorithms. This can be especially problematic with the very small feature sizes of the Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) currently used in these memory resources. With minimum feature sizes approaching 0.5 microns or less, failures are more likely to cluster within a particular physical area in the DRAM or SRAM, thus affecting several adjacent memory bit storage cells and causing multiple bit errors.